forked from forks/qmk_firmware
796 lines
27 KiB
C
796 lines
27 KiB
C
#include <ch.h>
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#include <hal.h>
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#include "eeconfig.h"
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/*************************************/
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/* Hardware backend */
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/* */
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/* Code from PJRC/Teensyduino */
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/*************************************/
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/* Teensyduino Core Library
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* http://www.pjrc.com/teensy/
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* Copyright (c) 2013 PJRC.COM, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* 1. The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* 2. If the Software is incorporated into a build system that allows
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* selection among a list of target devices, then similar target
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* devices manufactured by PJRC.COM must be included in the list of
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* target devices and selectable in the same manner.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#define SMC_PMSTAT_RUN ((uint8_t)0x01)
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#define SMC_PMSTAT_HSRUN ((uint8_t)0x80)
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#define F_CPU KINETIS_SYSCLK_FREQUENCY
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static inline int kinetis_hsrun_disable(void) {
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#if defined(MK66F18)
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if (SMC->PMSTAT == SMC_PMSTAT_HSRUN) {
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// First, reduce the CPU clock speed, but do not change
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// the peripheral speed (F_BUS). Serial1 & Serial2 baud
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// rates will be impacted, but most other peripherals
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// will continue functioning at the same speed.
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# if F_CPU == 256000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // TODO: TEST
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# elif F_CPU == 256000000 && F_BUS == 128000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // TODO: TEST
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# elif F_CPU == 240000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok
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# elif F_CPU == 240000000 && F_BUS == 80000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 240000000 && F_BUS == 120000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 216000000 && F_BUS == 54000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok
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# elif F_CPU == 216000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 216000000 && F_BUS == 108000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 192000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok
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# elif F_CPU == 192000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 192000000 && F_BUS == 96000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 180000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 180000000 && F_BUS == 90000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 168000000 && F_BUS == 56000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 5); // ok
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# elif F_CPU == 144000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 5); // ok
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# elif F_CPU == 144000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 5); // ok
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# elif F_CPU == 120000000 && F_BUS == 60000000
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2 - 1) |
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# if defined(MK66F18)
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SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3 - 1) |
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# endif
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SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
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# else
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return 0;
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# endif
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// Then turn off HSRUN mode
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SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(0);
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while (SMC->PMSTAT == SMC_PMSTAT_HSRUN)
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; // wait
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return 1;
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}
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#endif
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return 0;
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}
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static inline int kinetis_hsrun_enable(void) {
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#if defined(MK66F18)
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if (SMC->PMSTAT == SMC_PMSTAT_RUN) {
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// Turn HSRUN mode on
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SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(3);
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while (SMC->PMSTAT != SMC_PMSTAT_HSRUN) {
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;
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} // wait
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// Then configure clock for full speed
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# if F_CPU == 256000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7);
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# elif F_CPU == 256000000 && F_BUS == 128000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7);
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# elif F_CPU == 240000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7);
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# elif F_CPU == 240000000 && F_BUS == 80000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7);
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# elif F_CPU == 240000000 && F_BUS == 120000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7);
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# elif F_CPU == 216000000 && F_BUS == 54000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7);
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# elif F_CPU == 216000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7);
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# elif F_CPU == 216000000 && F_BUS == 108000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7);
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# elif F_CPU == 192000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 6);
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# elif F_CPU == 192000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 6);
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# elif F_CPU == 192000000 && F_BUS == 96000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 6);
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# elif F_CPU == 180000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 6);
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# elif F_CPU == 180000000 && F_BUS == 90000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 6);
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# elif F_CPU == 168000000 && F_BUS == 56000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 5);
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# elif F_CPU == 144000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 4);
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# elif F_CPU == 144000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 4);
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# elif F_CPU == 120000000 && F_BUS == 60000000
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2 - 1) |
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# if defined(MK66F18)
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SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3 - 1) |
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# endif
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SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
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# else
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return 0;
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# endif
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return 1;
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}
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#endif
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return 0;
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}
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#if defined(K20x) || defined(MK66F18) /* chip selection */
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/* Teensy 3.0, 3.1, 3.2; mchck; infinity keyboard */
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// The EEPROM is really RAM with a hardware-based backup system to
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// flash memory. Selecting a smaller size EEPROM allows more wear
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// leveling, for higher write endurance. If you edit this file,
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// set this to the smallest size your application can use. Also,
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// due to Freescale's implementation, writing 16 or 32 bit words
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// (aligned to 2 or 4 byte boundaries) has twice the endurance
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// compared to writing 8 bit bytes.
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//
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# ifndef EEPROM_SIZE
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# define EEPROM_SIZE 32
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# endif
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/*
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^^^ Here be dragons:
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NXP AppNote AN4282 section 3.1 states that partitioning must only be done once.
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Once EEPROM partitioning is done, the size is locked to this initial configuration.
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Attempts to modify the EEPROM_SIZE setting may brick your board.
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*/
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// Writing unaligned 16 or 32 bit data is handled automatically when
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// this is defined, but at a cost of extra code size. Without this,
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// any unaligned write will cause a hard fault exception! If you're
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// absolutely sure all 16 and 32 bit writes will be aligned, you can
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// remove the extra unnecessary code.
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//
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# define HANDLE_UNALIGNED_WRITES
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# if defined(K20x)
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# define EEPROM_MAX 2048
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# define EEPARTITION 0x03 // all 32K dataflash for EEPROM, none for Data
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# define EEESPLIT 0x30 // must be 0x30 on these chips
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# elif defined(MK66F18)
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# define EEPROM_MAX 4096
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# define EEPARTITION 0x05 // 128K dataflash for EEPROM, 128K for Data
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# define EEESPLIT 0x10 // best endurance: 0x00 = first 12%, 0x10 = first 25%, 0x30 = all equal
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# endif
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// Minimum EEPROM Endurance
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// ------------------------
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# if (EEPROM_SIZE == 4096)
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# define EEESIZE 0x02
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# elif (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word
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# define EEESIZE 0x03
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# elif (EEPROM_SIZE == 1024) // 75000 writes/byte or 150000 writes/word
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# define EEESIZE 0x04
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# elif (EEPROM_SIZE == 512) // 155000 writes/byte or 310000 writes/word
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# define EEESIZE 0x05
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# elif (EEPROM_SIZE == 256) // 315000 writes/byte or 630000 writes/word
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# define EEESIZE 0x06
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# elif (EEPROM_SIZE == 128) // 635000 writes/byte or 1270000 writes/word
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# define EEESIZE 0x07
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# elif (EEPROM_SIZE == 64) // 1275000 writes/byte or 2550000 writes/word
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# define EEESIZE 0x08
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# elif (EEPROM_SIZE == 32) // 2555000 writes/byte or 5110000 writes/word
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# define EEESIZE 0x09
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# endif
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/** \brief eeprom initialization
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*
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* FIXME: needs doc
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*/
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void eeprom_initialize(void) {
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uint32_t count = 0;
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uint16_t do_flash_cmd[] = {0xf06f, 0x037f, 0x7003, 0x7803, 0xf013, 0x0f80, 0xd0fb, 0x4770};
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uint8_t status;
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if (FTFL->FCNFG & FTFL_FCNFG_RAMRDY) {
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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// FlexRAM is configured as traditional RAM
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// We need to reconfigure for EEPROM usage
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kinetis_hsrun_disable();
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FTFL->FCCOB0 = 0x80; // PGMPART = Program Partition Command
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FTFL->FCCOB3 = 0;
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FTFL->FCCOB4 = EEESPLIT | EEESIZE;
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FTFL->FCCOB5 = EEPARTITION;
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__disable_irq();
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// do_flash_cmd() must execute from RAM. Luckily the C syntax is simple...
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(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFL->FSTAT));
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__enable_irq();
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kinetis_hsrun_enable();
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status = FTFL->FSTAT;
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if (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL)) {
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FTFL->FSTAT = (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL));
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return; // error
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}
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}
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// wait for eeprom to become ready (is this really necessary?)
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while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
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if (++count > 200000) break;
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}
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}
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# define FlexRAM ((volatile uint8_t *)0x14000000)
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/** \brief eeprom read byte
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*
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* FIXME: needs doc
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*/
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uint8_t eeprom_read_byte(const uint8_t *addr) {
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE) return 0;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return FlexRAM[offset];
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}
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/** \brief eeprom read word
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*
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* FIXME: needs doc
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*/
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uint16_t eeprom_read_word(const uint16_t *addr) {
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE - 1) return 0;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return *(uint16_t *)(&FlexRAM[offset]);
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}
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/** \brief eeprom read dword
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*
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* FIXME: needs doc
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*/
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uint32_t eeprom_read_dword(const uint32_t *addr) {
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE - 3) return 0;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return *(uint32_t *)(&FlexRAM[offset]);
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}
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/** \brief eeprom read block
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*
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* FIXME: needs doc
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*/
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void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
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uint32_t offset = (uint32_t)addr;
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uint8_t *dest = (uint8_t *)buf;
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uint32_t end = offset + len;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (end > EEPROM_SIZE) end = EEPROM_SIZE;
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while (offset < end) {
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*dest++ = FlexRAM[offset++];
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}
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}
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/** \brief eeprom is ready
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*
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* FIXME: needs doc
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*/
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int eeprom_is_ready(void) { return (FTFL->FCNFG & FTFL_FCNFG_EEERDY) ? 1 : 0; }
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/** \brief flexram wait
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*
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* FIXME: needs doc
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*/
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static void flexram_wait(void) {
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while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
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// TODO: timeout
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}
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}
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/** \brief eeprom_write_byte
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*
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* FIXME: needs doc
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*/
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void eeprom_write_byte(uint8_t *addr, uint8_t value) {
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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/** \brief eeprom write word
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*
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* FIXME: needs doc
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*/
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void eeprom_write_word(uint16_t *addr, uint16_t value) {
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE - 1) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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# ifdef HANDLE_UNALIGNED_WRITES
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if ((offset & 1) == 0) {
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# endif
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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# ifdef HANDLE_UNALIGNED_WRITES
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} else {
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (FlexRAM[offset + 1] != (value >> 8)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset + 1] = value >> 8;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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# endif
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}
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/** \brief eeprom write dword
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*
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* FIXME: needs doc
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*/
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void eeprom_write_dword(uint32_t *addr, uint32_t value) {
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE - 3) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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# ifdef HANDLE_UNALIGNED_WRITES
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switch (offset & 3) {
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case 0:
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# endif
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if (*(uint32_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint32_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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return;
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# ifdef HANDLE_UNALIGNED_WRITES
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case 2:
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16;
|
|
flexram_wait();
|
|
kinetis_hsrun_enable();
|
|
}
|
|
return;
|
|
default:
|
|
if (FlexRAM[offset] != value) {
|
|
kinetis_hsrun_disable();
|
|
uint8_t stat = FTFL->FSTAT & 0x70;
|
|
if (stat) FTFL->FSTAT = stat;
|
|
FlexRAM[offset] = value;
|
|
flexram_wait();
|
|
kinetis_hsrun_enable();
|
|
}
|
|
if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) {
|
|
kinetis_hsrun_disable();
|
|
uint8_t stat = FTFL->FSTAT & 0x70;
|
|
if (stat) FTFL->FSTAT = stat;
|
|
*(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8;
|
|
flexram_wait();
|
|
kinetis_hsrun_enable();
|
|
}
|
|
if (FlexRAM[offset + 3] != (value >> 24)) {
|
|
kinetis_hsrun_disable();
|
|
uint8_t stat = FTFL->FSTAT & 0x70;
|
|
if (stat) FTFL->FSTAT = stat;
|
|
FlexRAM[offset + 3] = value >> 24;
|
|
flexram_wait();
|
|
kinetis_hsrun_enable();
|
|
}
|
|
}
|
|
# endif
|
|
}
|
|
|
|
/** \brief eeprom write block
|
|
*
|
|
* FIXME: needs doc
|
|
*/
|
|
void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
|
uint32_t offset = (uint32_t)addr;
|
|
const uint8_t *src = (const uint8_t *)buf;
|
|
|
|
if (offset >= EEPROM_SIZE) return;
|
|
if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
|
|
if (len >= EEPROM_SIZE) len = EEPROM_SIZE;
|
|
if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset;
|
|
kinetis_hsrun_disable();
|
|
while (len > 0) {
|
|
uint32_t lsb = offset & 3;
|
|
if (lsb == 0 && len >= 4) {
|
|
// write aligned 32 bits
|
|
uint32_t val32;
|
|
val32 = *src++;
|
|
val32 |= (*src++ << 8);
|
|
val32 |= (*src++ << 16);
|
|
val32 |= (*src++ << 24);
|
|
if (*(uint32_t *)(&FlexRAM[offset]) != val32) {
|
|
uint8_t stat = FTFL->FSTAT & 0x70;
|
|
if (stat) FTFL->FSTAT = stat;
|
|
*(uint32_t *)(&FlexRAM[offset]) = val32;
|
|
flexram_wait();
|
|
}
|
|
offset += 4;
|
|
len -= 4;
|
|
} else if ((lsb == 0 || lsb == 2) && len >= 2) {
|
|
// write aligned 16 bits
|
|
uint16_t val16;
|
|
val16 = *src++;
|
|
val16 |= (*src++ << 8);
|
|
if (*(uint16_t *)(&FlexRAM[offset]) != val16) {
|
|
uint8_t stat = FTFL->FSTAT & 0x70;
|
|
if (stat) FTFL->FSTAT = stat;
|
|
*(uint16_t *)(&FlexRAM[offset]) = val16;
|
|
flexram_wait();
|
|
}
|
|
offset += 2;
|
|
len -= 2;
|
|
} else {
|
|
// write 8 bits
|
|
uint8_t val8 = *src++;
|
|
if (FlexRAM[offset] != val8) {
|
|
uint8_t stat = FTFL->FSTAT & 0x70;
|
|
if (stat) FTFL->FSTAT = stat;
|
|
FlexRAM[offset] = val8;
|
|
flexram_wait();
|
|
}
|
|
offset++;
|
|
len--;
|
|
}
|
|
}
|
|
kinetis_hsrun_enable();
|
|
}
|
|
|
|
/*
|
|
void do_flash_cmd(volatile uint8_t *fstat)
|
|
{
|
|
*fstat = 0x80;
|
|
while ((*fstat & 0x80) == 0) ; // wait
|
|
}
|
|
00000000 <do_flash_cmd>:
|
|
0: f06f 037f mvn.w r3, #127 ; 0x7f
|
|
4: 7003 strb r3, [r0, #0]
|
|
6: 7803 ldrb r3, [r0, #0]
|
|
8: f013 0f80 tst.w r3, #128 ; 0x80
|
|
c: d0fb beq.n 6 <do_flash_cmd+0x6>
|
|
e: 4770 bx lr
|
|
*/
|
|
|
|
#elif defined(KL2x) /* chip selection */
|
|
/* Teensy LC (emulated) */
|
|
|
|
# define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
|
|
|
|
extern uint32_t __eeprom_workarea_start__;
|
|
extern uint32_t __eeprom_workarea_end__;
|
|
|
|
# define EEPROM_SIZE 128
|
|
|
|
static uint32_t flashend = 0;
|
|
|
|
void eeprom_initialize(void) {
|
|
const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__);
|
|
|
|
do {
|
|
if (*p++ == 0xFFFF) {
|
|
flashend = (uint32_t)(p - 2);
|
|
return;
|
|
}
|
|
} while (p < (uint16_t *)SYMVAL(__eeprom_workarea_end__));
|
|
flashend = (uint32_t)(p - 1);
|
|
}
|
|
|
|
uint8_t eeprom_read_byte(const uint8_t *addr) {
|
|
uint32_t offset = (uint32_t)addr;
|
|
const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__);
|
|
const uint16_t *end = (const uint16_t *)((uint32_t)flashend);
|
|
uint16_t val;
|
|
uint8_t data = 0xFF;
|
|
|
|
if (!end) {
|
|
eeprom_initialize();
|
|
end = (const uint16_t *)((uint32_t)flashend);
|
|
}
|
|
if (offset < EEPROM_SIZE) {
|
|
while (p <= end) {
|
|
val = *p++;
|
|
if ((val & 255) == offset) data = val >> 8;
|
|
}
|
|
}
|
|
return data;
|
|
}
|
|
|
|
static void flash_write(const uint16_t *code, uint32_t addr, uint32_t data) {
|
|
// with great power comes great responsibility....
|
|
uint32_t stat;
|
|
*(uint32_t *)&(FTFA->FCCOB3) = 0x06000000 | (addr & 0x00FFFFFC);
|
|
*(uint32_t *)&(FTFA->FCCOB7) = data;
|
|
__disable_irq();
|
|
(*((void (*)(volatile uint8_t *))((uint32_t)code | 1)))(&(FTFA->FSTAT));
|
|
__enable_irq();
|
|
stat = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR | FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL);
|
|
if (stat) {
|
|
FTFA->FSTAT = stat;
|
|
}
|
|
MCM->PLACR |= MCM_PLACR_CFCC;
|
|
}
|
|
|
|
void eeprom_write_byte(uint8_t *addr, uint8_t data) {
|
|
uint32_t offset = (uint32_t)addr;
|
|
const uint16_t *p, *end = (const uint16_t *)((uint32_t)flashend);
|
|
uint32_t i, val, flashaddr;
|
|
uint16_t do_flash_cmd[] = {0x2380, 0x7003, 0x7803, 0xb25b, 0x2b00, 0xdafb, 0x4770};
|
|
uint8_t buf[EEPROM_SIZE];
|
|
|
|
if (offset >= EEPROM_SIZE) return;
|
|
if (!end) {
|
|
eeprom_initialize();
|
|
end = (const uint16_t *)((uint32_t)flashend);
|
|
}
|
|
if (++end < (uint16_t *)SYMVAL(__eeprom_workarea_end__)) {
|
|
val = (data << 8) | offset;
|
|
flashaddr = (uint32_t)end;
|
|
flashend = flashaddr;
|
|
if ((flashaddr & 2) == 0) {
|
|
val |= 0xFFFF0000;
|
|
} else {
|
|
val <<= 16;
|
|
val |= 0x0000FFFF;
|
|
}
|
|
flash_write(do_flash_cmd, flashaddr, val);
|
|
} else {
|
|
for (i = 0; i < EEPROM_SIZE; i++) {
|
|
buf[i] = 0xFF;
|
|
}
|
|
val = 0;
|
|
for (p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); p < (uint16_t *)SYMVAL(__eeprom_workarea_end__); p++) {
|
|
val = *p;
|
|
if ((val & 255) < EEPROM_SIZE) {
|
|
buf[val & 255] = val >> 8;
|
|
}
|
|
}
|
|
buf[offset] = data;
|
|
for (flashaddr = (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); flashaddr < (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_end__); flashaddr += 1024) {
|
|
*(uint32_t *)&(FTFA->FCCOB3) = 0x09000000 | flashaddr;
|
|
__disable_irq();
|
|
(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFA->FSTAT));
|
|
__enable_irq();
|
|
val = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR | FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL);
|
|
;
|
|
if (val) FTFA->FSTAT = val;
|
|
MCM->PLACR |= MCM_PLACR_CFCC;
|
|
}
|
|
flashaddr = (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__);
|
|
for (i = 0; i < EEPROM_SIZE; i++) {
|
|
if (buf[i] == 0xFF) continue;
|
|
if ((flashaddr & 2) == 0) {
|
|
val = (buf[i] << 8) | i;
|
|
} else {
|
|
val = val | (buf[i] << 24) | (i << 16);
|
|
flash_write(do_flash_cmd, flashaddr, val);
|
|
}
|
|
flashaddr += 2;
|
|
}
|
|
flashend = flashaddr;
|
|
if ((flashaddr & 2)) {
|
|
val |= 0xFFFF0000;
|
|
flash_write(do_flash_cmd, flashaddr, val);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
void do_flash_cmd(volatile uint8_t *fstat)
|
|
{
|
|
*fstat = 0x80;
|
|
while ((*fstat & 0x80) == 0) ; // wait
|
|
}
|
|
00000000 <do_flash_cmd>:
|
|
0: 2380 movs r3, #128 ; 0x80
|
|
2: 7003 strb r3, [r0, #0]
|
|
4: 7803 ldrb r3, [r0, #0]
|
|
6: b25b sxtb r3, r3
|
|
8: 2b00 cmp r3, #0
|
|
a: dafb bge.n 4 <do_flash_cmd+0x4>
|
|
c: 4770 bx lr
|
|
*/
|
|
|
|
uint16_t eeprom_read_word(const uint16_t *addr) {
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
|
|
}
|
|
|
|
uint32_t eeprom_read_dword(const uint32_t *addr) {
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
|
|
}
|
|
|
|
void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
uint8_t * dest = (uint8_t *)buf;
|
|
while (len--) {
|
|
*dest++ = eeprom_read_byte(p++);
|
|
}
|
|
}
|
|
|
|
int eeprom_is_ready(void) { return 1; }
|
|
|
|
void eeprom_write_word(uint16_t *addr, uint16_t value) {
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p, value >> 8);
|
|
}
|
|
|
|
void eeprom_write_dword(uint32_t *addr, uint32_t value) {
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p++, value >> 8);
|
|
eeprom_write_byte(p++, value >> 16);
|
|
eeprom_write_byte(p, value >> 24);
|
|
}
|
|
|
|
void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
|
uint8_t * p = (uint8_t *)addr;
|
|
const uint8_t *src = (const uint8_t *)buf;
|
|
while (len--) {
|
|
eeprom_write_byte(p++, *src++);
|
|
}
|
|
}
|
|
|
|
#else
|
|
// No EEPROM supported, so emulate it
|
|
|
|
# ifndef EEPROM_SIZE
|
|
# include "eeconfig.h"
|
|
# define EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO
|
|
# endif
|
|
__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE];
|
|
|
|
uint8_t eeprom_read_byte(const uint8_t *addr) {
|
|
uint32_t offset = (uint32_t)addr;
|
|
return buffer[offset];
|
|
}
|
|
|
|
void eeprom_write_byte(uint8_t *addr, uint8_t value) {
|
|
uint32_t offset = (uint32_t)addr;
|
|
buffer[offset] = value;
|
|
}
|
|
|
|
uint16_t eeprom_read_word(const uint16_t *addr) {
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
|
|
}
|
|
|
|
uint32_t eeprom_read_dword(const uint32_t *addr) {
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
|
|
}
|
|
|
|
void eeprom_read_block(void *buf, const void *addr, size_t len) {
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
uint8_t * dest = (uint8_t *)buf;
|
|
while (len--) {
|
|
*dest++ = eeprom_read_byte(p++);
|
|
}
|
|
}
|
|
|
|
void eeprom_write_word(uint16_t *addr, uint16_t value) {
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p, value >> 8);
|
|
}
|
|
|
|
void eeprom_write_dword(uint32_t *addr, uint32_t value) {
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p++, value >> 8);
|
|
eeprom_write_byte(p++, value >> 16);
|
|
eeprom_write_byte(p, value >> 24);
|
|
}
|
|
|
|
void eeprom_write_block(const void *buf, void *addr, size_t len) {
|
|
uint8_t * p = (uint8_t *)addr;
|
|
const uint8_t *src = (const uint8_t *)buf;
|
|
while (len--) {
|
|
eeprom_write_byte(p++, *src++);
|
|
}
|
|
}
|
|
|
|
#endif /* chip selection */
|
|
// The update functions just calls write for now, but could probably be optimized
|
|
|
|
void eeprom_update_byte(uint8_t *addr, uint8_t value) { eeprom_write_byte(addr, value); }
|
|
|
|
void eeprom_update_word(uint16_t *addr, uint16_t value) {
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p, value >> 8);
|
|
}
|
|
|
|
void eeprom_update_dword(uint32_t *addr, uint32_t value) {
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p++, value >> 8);
|
|
eeprom_write_byte(p++, value >> 16);
|
|
eeprom_write_byte(p, value >> 24);
|
|
}
|
|
|
|
void eeprom_update_block(const void *buf, void *addr, size_t len) {
|
|
uint8_t * p = (uint8_t *)addr;
|
|
const uint8_t *src = (const uint8_t *)buf;
|
|
while (len--) {
|
|
eeprom_write_byte(p++, *src++);
|
|
}
|
|
}
|