forked from forks/qmk_firmware
210 lines
7.6 KiB
C
210 lines
7.6 KiB
C
/* Copyright 2018 Jack Humbert
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* Copyright 2018 Yiancar
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* Copyright 2023 customMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This library is only valid for STM32 processors.
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* This library follows the convention of the AVR i2c_master library.
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* As a result addresses are expected to be already shifted (addr << 1).
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* I2CD1 is the default driver which corresponds to pins B6 and B7. This
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* can be changed.
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* Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
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* STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
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* but using any other I2C pins should be trivial.
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*/
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#include "i2c_master.h"
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#include "gpio.h"
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#include "chibios_config.h"
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#include <string.h>
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#include <ch.h>
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#include <hal.h>
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#ifndef I2C1_SCL_PIN
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# define I2C1_SCL_PIN B6
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#endif
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#ifndef I2C1_SDA_PIN
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# define I2C1_SDA_PIN B7
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#endif
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#ifdef USE_I2CV1
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# ifndef I2C1_OPMODE
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# define I2C1_OPMODE OPMODE_I2C
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# endif
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# ifndef I2C1_CLOCK_SPEED
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# define I2C1_CLOCK_SPEED 100000 /* 400000 */
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# endif
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# ifndef I2C1_DUTY_CYCLE
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# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
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# endif
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#else
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// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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# ifndef I2C1_TIMINGR_PRESC
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# define I2C1_TIMINGR_PRESC 0U
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# endif
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# ifndef I2C1_TIMINGR_SCLDEL
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# define I2C1_TIMINGR_SCLDEL 7U
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# endif
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# ifndef I2C1_TIMINGR_SDADEL
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# define I2C1_TIMINGR_SDADEL 0U
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# endif
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# ifndef I2C1_TIMINGR_SCLH
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# define I2C1_TIMINGR_SCLH 38U
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# endif
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# ifndef I2C1_TIMINGR_SCLL
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# define I2C1_TIMINGR_SCLL 129U
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# endif
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#endif
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#ifndef I2C_DRIVER
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# define I2C_DRIVER I2CD1
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#endif
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#ifdef USE_GPIOV1
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# ifndef I2C1_SCL_PAL_MODE
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# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
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# endif
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# ifndef I2C1_SDA_PAL_MODE
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# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
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# endif
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#else
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// The default PAL alternate modes are used to signal that the pins are used for I2C
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# ifndef I2C1_SCL_PAL_MODE
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# define I2C1_SCL_PAL_MODE 4
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# endif
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# ifndef I2C1_SDA_PAL_MODE
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# define I2C1_SDA_PAL_MODE 4
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# endif
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#endif
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static const I2CConfig i2cconfig = {
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#if defined(USE_I2CV1_CONTRIB)
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I2C1_CLOCK_SPEED,
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#elif defined(USE_I2CV1)
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I2C1_OPMODE,
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I2C1_CLOCK_SPEED,
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I2C1_DUTY_CYCLE,
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#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
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I2C1_OPMODE,
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I2C1_CLOCK_SPEED,
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#else
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// This configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) | STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) | STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL), 0, 0
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#endif
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};
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/**
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* @brief Handles any I2C error condition by stopping the I2C peripheral and
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* aborting any ongoing transactions. Furthermore ChibiOS status codes are
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* converted into QMK codes.
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*
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* @param status ChibiOS specific I2C status code
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* @return i2c_status_t QMK specific I2C status code
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*/
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static i2c_status_t i2c_epilogue(const msg_t status) {
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if (status == MSG_OK) {
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return I2C_STATUS_SUCCESS;
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}
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// From ChibiOS HAL: "After a timeout the driver must be stopped and
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// restarted because the bus is in an uncertain state." We also issue that
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// hard stop in case of any error.
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i2cStop(&I2C_DRIVER);
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return status == MSG_TIMEOUT ? I2C_STATUS_TIMEOUT : I2C_STATUS_ERROR;
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}
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__attribute__((weak)) void i2c_init(void) {
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static bool is_initialised = false;
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if (!is_initialised) {
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is_initialised = true;
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// Try releasing special pins for a short time
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palSetLineMode(I2C1_SCL_PIN, PAL_MODE_INPUT);
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palSetLineMode(I2C1_SDA_PIN, PAL_MODE_INPUT);
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chThdSleepMilliseconds(10);
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#if defined(USE_GPIOV1)
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palSetLineMode(I2C1_SCL_PIN, I2C1_SCL_PAL_MODE);
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palSetLineMode(I2C1_SDA_PIN, I2C1_SDA_PAL_MODE);
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#else
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palSetLineMode(I2C1_SCL_PIN, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
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palSetLineMode(I2C1_SDA_PIN, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
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#endif
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}
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}
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (address >> 1), data, length, 0, 0, TIME_MS2I(timeout));
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return i2c_epilogue(status);
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}
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (address >> 1), data, length, TIME_MS2I(timeout));
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return i2c_epilogue(status);
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}
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i2c_status_t i2c_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2cStart(&I2C_DRIVER, &i2cconfig);
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uint8_t complete_packet[length + 1];
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for (uint16_t i = 0; i < length; i++) {
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complete_packet[i + 1] = data[i];
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}
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complete_packet[0] = regaddr;
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), complete_packet, length + 1, 0, 0, TIME_MS2I(timeout));
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return i2c_epilogue(status);
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}
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i2c_status_t i2c_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2cStart(&I2C_DRIVER, &i2cconfig);
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uint8_t complete_packet[length + 2];
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for (uint16_t i = 0; i < length; i++) {
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complete_packet[i + 2] = data[i];
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}
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complete_packet[0] = regaddr >> 8;
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complete_packet[1] = regaddr & 0xFF;
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), complete_packet, length + 2, 0, 0, TIME_MS2I(timeout));
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return i2c_epilogue(status);
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}
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i2c_status_t i2c_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), ®addr, 1, data, length, TIME_MS2I(timeout));
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return i2c_epilogue(status);
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}
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i2c_status_t i2c_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2cStart(&I2C_DRIVER, &i2cconfig);
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uint8_t register_packet[2] = {regaddr >> 8, regaddr & 0xFF};
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), register_packet, 2, data, length, TIME_MS2I(timeout));
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return i2c_epilogue(status);
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}
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__attribute__((weak)) i2c_status_t i2c_ping_address(uint8_t address, uint16_t timeout) {
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// ChibiOS does not provide low level enough control to check for an ack.
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// Best effort instead tries reading register 0 which will either succeed or timeout.
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// This approach may produce false negative results for I2C devices that do not respond to a register 0 read request.
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uint8_t data = 0;
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return i2c_read_register(address, 0, &data, sizeof(data), timeout);
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} |