forked from forks/qmk_firmware
160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
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/* This is from http://www.mtcnet.net/~henryvm/wdt/ */
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#ifndef _AVR_WD_H_
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#define _AVR_WD_H_
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#include <avr/io.h>
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/*
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Copyright (c) 2009, Curt Van Maanen
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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include usage-
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#include "wd.h" //if in same directory as project
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#include <avr/wd.h> //if wd.h is in avr directory
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set watchdog modes and prescale
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usage-
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WD_SET(mode,[timeout]); //prescale always set
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modes-
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WD_OFF disabled
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WD_RST normal reset mode
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WD_IRQ interrupt only mode (if supported)
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WD_RST_IRQ interrupt+reset mode (if supported)
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timeout-
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WDTO_15MS default if no timeout provided
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WDTO_30MS
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WDTO_60MS
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WDTO_120MS
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WDTO_250MS
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WDTO_500MS
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WDTO_1S
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WDTO_2S
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WDTO_4S (if supported)
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WDTO_8S (if supported)
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examples-
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WD_SET(WD_RST,WDTO_1S); //reset mode, 1s timeout
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WD_SET(WD_OFF); //watchdog disabled (if not fused on)
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WD_SET(WD_RST); //reset mode, 15ms (default timeout)
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WD_SET(WD_IRQ,WDTO_120MS); //interrupt only mode, 120ms timeout
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WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout
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for enhanced watchdogs, if the watchdog is not being used WDRF should be
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cleared on every power up or reset, along with disabling the watchdog-
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WD_DISABLE(); //clear WDRF, then turn off watchdog
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*/
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//reset registers to the same name (MCUCSR)
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#if !defined(MCUCSR)
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#define MCUCSR MCUSR
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#endif
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//watchdog registers to the same name (WDTCSR)
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#if !defined(WDTCSR)
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#define WDTCSR WDTCR
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#endif
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//if enhanced watchdog, define irq values, create disable macro
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#if defined(WDIF)
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#define WD_IRQ 0xC0
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#define WD_RST_IRQ 0xC8
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#define WD_DISABLE() do{ \
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MCUCSR &= ~(1<<WDRF); \
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WD_SET(WD_OFF); \
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}while(0)
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#endif
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//all watchdogs
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#define WD_RST 8
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#define WD_OFF 0
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//prescale values
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#define WDTO_15MS 0
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#define WDTO_30MS 1
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#define WDTO_60MS 2
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#define WDTO_120MS 3
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#define WDTO_250MS 4
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#define WDTO_500MS 5
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#define WDTO_1S 6
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#define WDTO_2S 7
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//prescale values for avrs with WDP3
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#if defined(WDP3)
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#define WDTO_4S 0x20
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#define WDTO_8S 0x21
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#endif
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//watchdog reset
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#define WDR() __asm__ __volatile__("wdr")
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//avr reset using watchdog
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#define WD_AVR_RESET() do{ \
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__asm__ __volatile__("cli"); \
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WD_SET_UNSAFE(WD_RST); \
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while(1); \
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}while(0)
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/*set the watchdog-
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1. save SREG
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2. turn off irq's
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3. reset watchdog timer
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4. enable watchdog change
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5. write watchdog value
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6. restore SREG (restoring irq status)
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*/
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#define WD_SET(val,...) \
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__asm__ __volatile__( \
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"in __tmp_reg__,__SREG__" "\n\t" \
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"cli" "\n\t" \
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"wdr" "\n\t" \
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"sts %[wdreg],%[wden]" "\n\t" \
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"sts %[wdreg],%[wdval]" "\n\t" \
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"out __SREG__,__tmp_reg__" "\n\t" \
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: \
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: [wdreg] "M" (&WDTCSR), \
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[wden] "r" ((uint8_t)(0x18)), \
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[wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
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: "r0" \
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)
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/*set the watchdog when I bit in SREG known to be clear-
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1. reset watchdog timer
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2. enable watchdog change
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5. write watchdog value
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*/
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#define WD_SET_UNSAFE(val,...) \
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__asm__ __volatile__( \
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"wdr" "\n\t" \
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"sts %[wdreg],%[wden]" "\n\t" \
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"sts %[wdreg],%[wdval]" "\n\t" \
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: \
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: [wdreg] "M" (&WDTCSR), \
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[wden] "r" ((uint8_t)(0x18)), \
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[wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
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)
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//for compatibility with avr/wdt.h
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#define wdt_enable(val) WD_SET(WD_RST,val)
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#define wdt_disable() WD_SET(WD_OFF)
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#endif /* _AVR_WD_H_ */
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