forked from forks/qmk_firmware
232 lines
8.8 KiB
C
232 lines
8.8 KiB
C
|
// Copyright 2022 Mega Mind (@megamind4089)
|
||
|
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||
|
|
|
||
|
|
#ifndef MCUCONF_H
|
||
|
|
#define MCUCONF_H
|
||
|
|
|
||
|
|
/*
|
||
|
|
* STM32F4xx drivers configuration.
|
||
|
|
* The following settings override the default settings present in
|
||
|
|
* the various device driver implementation headers.
|
||
|
|
* Note that the settings for each driver only have effect if the whole
|
||
|
|
* driver is enabled in halconf.h.
|
||
|
|
*
|
||
|
|
* IRQ priorities:
|
||
|
|
* 15...0 Lowest...Highest.
|
||
|
|
*
|
||
|
|
* DMA priorities:
|
||
|
|
* 0...3 Lowest...Highest.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define STM32F4xx_MCUCONF
|
||
|
|
#define STM32F411_MCUCONF
|
||
|
|
|
||
|
|
/*
|
||
|
|
* HAL driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_NO_INIT FALSE
|
||
|
|
#define STM32_PVD_ENABLE FALSE
|
||
|
|
#define STM32_PLS STM32_PLS_LEV0
|
||
|
|
#define STM32_BKPRAM_ENABLE FALSE
|
||
|
|
#define STM32_HSI_ENABLED TRUE
|
||
|
|
#define STM32_LSI_ENABLED TRUE
|
||
|
|
#define STM32_HSE_ENABLED TRUE
|
||
|
|
#define STM32_LSE_ENABLED FALSE
|
||
|
|
#define STM32_CLOCK48_REQUIRED TRUE
|
||
|
|
#define STM32_SW STM32_SW_PLL
|
||
|
|
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||
|
|
#define STM32_PLLM_VALUE 8
|
||
|
|
#define STM32_PLLN_VALUE 336
|
||
|
|
#define STM32_PLLP_VALUE 4
|
||
|
|
#define STM32_PLLQ_VALUE 7
|
||
|
|
#define STM32_HPRE STM32_HPRE_DIV1
|
||
|
|
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||
|
|
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||
|
|
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||
|
|
#define STM32_RTCPRE_VALUE 8
|
||
|
|
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
|
||
|
|
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
|
||
|
|
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
|
||
|
|
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
|
||
|
|
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||
|
|
#define STM32_PLLI2SN_VALUE 192
|
||
|
|
#define STM32_PLLI2SR_VALUE 5
|
||
|
|
|
||
|
|
/*
|
||
|
|
* IRQ system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_IRQ_EXTI0_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI1_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI2_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI3_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI4_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI5_9_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI10_15_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI16_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI17_PRIORITY 15
|
||
|
|
#define STM32_IRQ_EXTI18_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI19_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI20_PRIORITY 6
|
||
|
|
#define STM32_IRQ_EXTI21_PRIORITY 15
|
||
|
|
#define STM32_IRQ_EXTI22_PRIORITY 15
|
||
|
|
|
||
|
|
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM1_CC_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM2_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM3_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM4_PRIORITY 7
|
||
|
|
#define STM32_IRQ_TIM5_PRIORITY 7
|
||
|
|
|
||
|
|
#define STM32_IRQ_USART1_PRIORITY 12
|
||
|
|
#define STM32_IRQ_USART2_PRIORITY 12
|
||
|
|
#define STM32_IRQ_USART6_PRIORITY 12
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ADC driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||
|
|
#define STM32_ADC_USE_ADC1 FALSE
|
||
|
|
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||
|
|
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||
|
|
#define STM32_ADC_IRQ_PRIORITY 6
|
||
|
|
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GPT driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_GPT_USE_TIM1 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM2 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM3 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM4 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM5 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM9 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM10 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM11 FALSE
|
||
|
|
|
||
|
|
/*
|
||
|
|
* I2C driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_I2C_USE_I2C1 TRUE
|
||
|
|
#define STM32_I2C_USE_I2C2 FALSE
|
||
|
|
#define STM32_I2C_USE_I2C3 FALSE
|
||
|
|
#define STM32_I2C_BUSY_TIMEOUT 50
|
||
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||
|
|
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||
|
|
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||
|
|
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||
|
|
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||
|
|
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||
|
|
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||
|
|
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* I2S driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_I2S_USE_SPI2 FALSE
|
||
|
|
#define STM32_I2S_USE_SPI3 FALSE
|
||
|
|
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
|
||
|
|
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
|
||
|
|
#define STM32_I2S_SPI2_DMA_PRIORITY 1
|
||
|
|
#define STM32_I2S_SPI3_DMA_PRIORITY 1
|
||
|
|
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
|
|
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ICU driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ICU_USE_TIM1 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM2 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM3 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM4 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM5 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM9 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM10 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM11 FALSE
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PWM driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_PWM_USE_TIM1 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM2 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM3 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM4 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM5 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM9 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM10 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM11 FALSE
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SERIAL driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SERIAL_USE_USART1 TRUE
|
||
|
|
#define STM32_SERIAL_USE_USART2 TRUE
|
||
|
|
#define STM32_SERIAL_USE_USART6 FALSE
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SPI driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SPI_USE_SPI1 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI2 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI3 FALSE
|
||
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ST driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ST_IRQ_PRIORITY 8
|
||
|
|
#define STM32_ST_USE_TIMER 2
|
||
|
|
|
||
|
|
/*
|
||
|
|
* UART driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_UART_USE_USART1 FALSE
|
||
|
|
#define STM32_UART_USE_USART2 FALSE
|
||
|
|
#define STM32_UART_USE_USART6 FALSE
|
||
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||
|
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||
|
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||
|
|
|
||
|
|
/*
|
||
|
|
* USB driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_USB_USE_OTG1 TRUE
|
||
|
|
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||
|
|
#define STM32_USB_HOST_WAKEUP_DURATION 2
|
||
|
|
|
||
|
|
/*
|
||
|
|
* WDG driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_WDG_USE_IWDG FALSE
|
||
|
|
|
||
|
|
#endif /* MCUCONF_H */
|