varl/qmk_firmware
1
0
Fork 0
forked from forks/qmk_firmware
Code Pull requests Activity

Correct ARM STM32 I2C frequency. (#7080)

Browse source 
It was beleaved that this setting result in a 400Khz I2C bus.

This was incorrect, actual frequency measure with a logic analyzer was around 150Khz.

This is derived from the excel sheet linked in the .h file.
Also confirmed with the ST IDE.
This commit is contained in:
yiancar 2019-10-31 16:19:57 +00:00 committed by Yan-Fa Li
parent 2ce6adff2b
commit 1acafc94f4
1 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
drivers/arm/i2c_master.h
View file

@ -73,19 +73,19 @@
// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
# ifndef I2C1_TIMINGR_PRESC # ifndef I2C1_TIMINGR_PRESC
# define I2C1_TIMINGR_PRESC 15U # define I2C1_TIMINGR_PRESC 0U
# endif # endif
# ifndef I2C1_TIMINGR_SCLDEL # ifndef I2C1_TIMINGR_SCLDEL
# define I2C1_TIMINGR_SCLDEL 4U # define I2C1_TIMINGR_SCLDEL 7U
# endif # endif
# ifndef I2C1_TIMINGR_SDADEL # ifndef I2C1_TIMINGR_SDADEL
# define I2C1_TIMINGR_SDADEL 2U # define I2C1_TIMINGR_SDADEL 0U
# endif # endif
# ifndef I2C1_TIMINGR_SCLH # ifndef I2C1_TIMINGR_SCLH
# define I2C1_TIMINGR_SCLH 15U # define I2C1_TIMINGR_SCLH 38U
# endif # endif
# ifndef I2C1_TIMINGR_SCLL # ifndef I2C1_TIMINGR_SCLL
# define I2C1_TIMINGR_SCLL 21U # define I2C1_TIMINGR_SCLL 129U
# endif # endif
#endif #endif