forked from forks/qmk_firmware
135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
#include "quantum.h"
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#if defined(__AVR__)
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# include <avr/io.h>
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# include <avr/interrupt.h>
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#endif
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#define ROWS_PER_HAND (MATRIX_ROWS / 2)
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#define SLAVE_MATRIX_SYNC_ADDR (0x01)
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typedef struct {
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char* buffer;
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size_t count;
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bool* flag;
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} transmit_status;
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transmit_status irx = {}, itx = {};
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// Buffer for master/slave matrix scan transmit.
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// Master: receive buffer.
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// Slave: transmit buffer.
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matrix_row_t sync_matrix[ROWS_PER_HAND];
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bool matrix_synced = false;
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void USART_init(uint16_t baud) {
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cli();
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// UBRR1H = (unsigned char)(baud >>8);
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// UBRR1L = (unsigned char)(baud);
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UBRR1 = baud;
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// Enable U2X1 for double speed.
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UCSR1A = (1 << U2X1);
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// Enable RX/TX, 9N1 mode
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UCSR1B = (1 << RXEN1) | (1 << TXEN1) | (1 << RXCIE1) | (1 << TXCIE1) | (1 << UCSZ12);
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UCSR1C = (1 << UCSZ10) | (1 << UCSZ11);
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sei();
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}
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ISR(USART1_RX_vect) {
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// read data from reg.
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uint8_t status = UCSR1A;
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uint8_t high_bit = UCSR1B;
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uint8_t low_data = UDR1;
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if (status & ((1 << FE1) | (1 << DOR1) | (1 << UPE1))) {
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// Something error happen, ignore this package.
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irx.count = 0;
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return;
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}
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// Is it a addr? (9th bit is one/zero?)
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if (high_bit & (1 << RXB81)) {
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// data is addr. prepend for receive.
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switch (low_data) {
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case SLAVE_MATRIX_SYNC_ADDR:
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irx.buffer = (char *)sync_matrix;
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irx.count = sizeof(sync_matrix) * sizeof(matrix_row_t);
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irx.flag = &matrix_synced;
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break;
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default:
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// ignore this package.
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irx.count = 0;
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break;
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}
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} else if (irx.count > 0) {
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*irx.buffer = low_data;
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++irx.buffer;
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if (--irx.count == 0 && irx.flag != NULL) {
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*irx.flag = true;
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}
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}
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}
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// TX complete
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ISR(USART1_TX_vect) {
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// Is in transmit?
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if (itx.count > 0) {
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// Send data.
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UCSR1B &= ~(1 << TXB81);
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UDR1 = *itx.buffer;
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// Move to next char.
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++itx.buffer;
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if (--itx.count == 0) {
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*itx.flag = true;
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}
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}
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// TODO: read queue/register for next message.
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}
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// return: queue depth.
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int send_packet(uint8_t addr, char* buffer, size_t length, bool* flag) {
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// See if we can start transmit right now.
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if ((itx.count == 0) && (UCSR1A & (1 << UDRE1))) {
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// Ready to write.
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// Prepend registers.
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itx.buffer = buffer;
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itx.count = length;
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itx.flag = flag;
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// Write addr to kick start transmit.
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UCSR1B |= (1 << TXB81);
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UDR1 = addr;
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// TODO: put request in queue;
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// }else{
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}
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return 0;
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}
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void transport_master_init(void) { USART_init(0); }
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void transport_slave_init(void) { USART_init(0); }
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// returns false if valid data not received from slave
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bool transport_master(matrix_row_t matrix[]) {
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if (matrix_synced) {
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for (uint8_t i = 0; i < ROWS_PER_HAND; ++i) {
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matrix[i] = sync_matrix[i];
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}
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matrix_synced = false;
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return true;
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}
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return false;
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}
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void transport_slave(matrix_row_t matrix[]) {
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for (uint8_t i = 0; i < ROWS_PER_HAND; ++i) {
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sync_matrix[i] = matrix[i];
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}
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matrix_synced = false;
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send_packet(SLAVE_MATRIX_SYNC_ADDR, (char*)sync_matrix, sizeof(sync_matrix) * sizeof(matrix_row_t), &matrix_synced);
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}
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